From b04d4d45e4529cfcaa997885ad93e0c68931b9a7 Mon Sep 17 00:00:00 2001 From: Matt Mullins Date: Sat, 22 Dec 2012 20:53:09 -0800 Subject: [PATCH] Set up the system clock to use crystal, and PLL to 80MHz --- led_blink.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/led_blink.c b/led_blink.c index 14ee0d1..657255a 100644 --- a/led_blink.c +++ b/led_blink.c @@ -5,6 +5,29 @@ static void spin(int); __attribute__((isr)) void main_isr() { + // Power on the PLL, set to 16MHz XTAL + SYSCTL_RCC_R &= ~(SYSCTL_RCC_PWRDN | SYSCTL_RCC_XTAL_M); + SYSCTL_RCC_R |= SYSCTL_RCC_XTAL_16MHZ; + + // Choose the main oscillator + SYSCTL_RCC_R &= ~(SYSCTL_RCC_MOSCDIS | SYSCTL_RCC_OSCSRC_M); + + // Wait for PLL to come up + while (!SYSCTL_PLLSTAT_R & SYSCTL_PLLSTAT_LOCK) { + asm(""); + } + + // Choose the PLL, at 80MHz + // Must re-do the OSCSRC, PWRDN configuration from RCC into RCC2, so + // that we don't interrupt what we've already configured. + int rcc2 = SYSCTL_RCC2_R; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB | + SYSCTL_RCC2_PWRDN2 | SYSCTL_RCC2_BYPASS2 | + SYSCTL_RCC2_OSCSRC2_M); + rcc2 |= SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_DIV400 | + (2 << SYSCTL_RCC2_SYSDIV2_S); + SYSCTL_RCC2_R = rcc2; + // Enable Port F SYSCTL_RCGCGPIO_R = 0x20; -- 2.11.0