From: Matt Mullins <mmullins@mmlx.us>
Date: Sun, 23 Dec 2012 04:53:09 +0000 (-0800)
Subject: Set up the system clock to use crystal, and PLL to 80MHz
X-Git-Url: http://git.mmlx.us/?a=commitdiff_plain;h=b04d4d45e4529cfcaa997885ad93e0c68931b9a7;p=stellaris%2Fled_blink.git

Set up the system clock to use crystal, and PLL to 80MHz
---

diff --git a/led_blink.c b/led_blink.c
index 14ee0d1..657255a 100644
--- a/led_blink.c
+++ b/led_blink.c
@@ -5,6 +5,29 @@ static void spin(int);
 
 __attribute__((isr))
 void main_isr() {
+	// Power on the PLL, set to 16MHz XTAL
+	SYSCTL_RCC_R &= ~(SYSCTL_RCC_PWRDN | SYSCTL_RCC_XTAL_M);
+	SYSCTL_RCC_R |= SYSCTL_RCC_XTAL_16MHZ;
+
+	// Choose the main oscillator
+	SYSCTL_RCC_R &= ~(SYSCTL_RCC_MOSCDIS | SYSCTL_RCC_OSCSRC_M);
+
+	// Wait for PLL to come up
+	while (!SYSCTL_PLLSTAT_R & SYSCTL_PLLSTAT_LOCK) {
+		asm("");
+	}
+
+	// Choose the PLL, at 80MHz
+	// Must re-do the OSCSRC, PWRDN configuration from RCC into RCC2, so
+	// that we don't interrupt what we've already configured.
+	int rcc2 = SYSCTL_RCC2_R;
+	rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB |
+	          SYSCTL_RCC2_PWRDN2 | SYSCTL_RCC2_BYPASS2 |
+	          SYSCTL_RCC2_OSCSRC2_M);
+	rcc2 |= SYSCTL_RCC2_USERCC2 | SYSCTL_RCC2_DIV400 |
+	        (2 << SYSCTL_RCC2_SYSDIV2_S);
+	SYSCTL_RCC2_R = rcc2;
+
 	// Enable Port F
 	SYSCTL_RCGCGPIO_R = 0x20;