This should be used instead of hard coding the corresponding platforms.
The feature test macro is needed to support different SOCs in a single
kernel image. While at it rename dma-mx1-mx2 to dma-v1 as mx25 doesn't
use it and so the mx2 part is wrong and move the header to
arch/arm/mach-imx.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+config IMX_HAVE_DMA_V1
+ bool
+
if ARCH_MX1
config SOC_IMX1
select CPU_ARM920T
+ select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
config SOC_IMX21
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
+ select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
config SOC_IMX27
select CPU_ARM926T
select ARCH_MXC_AUDMUX_V1
+ select IMX_HAVE_DMA_V1
select IMX_HAVE_IOMUX_V1
bool
obj-y := devices.o
+obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
+
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
/*
- * linux/arch/arm/plat-mxc/dma-mx1-mx2.c
+ * linux/arch/arm/plat-mxc/dma-v1.c
*
* i.MX DMA registration and IRQ dispatching
*
#include <asm/system.h>
#include <asm/irq.h>
#include <mach/hardware.h>
-#include <mach/dma-mx1-mx2.h>
+#include <mach/dma-v1.h>
#define DMA_DCR 0x00 /* Control Register */
#define DMA_DISR 0x04 /* Interrupt status Register */
--- /dev/null
+#ifndef __MACH_DMA_MX1_MX2_H__
+#define __MACH_DMA_MX1_MX2_H__
+/*
+ * Don't use this header in new code, it will go away when all users are
+ * converted to mach/dma-v1.h
+ */
+
+#include <mach/dma-v1.h>
+
+#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
/*
- * linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+ * linux/arch/arm/mach-imx/include/mach/dma-v1.h
*
* i.MX DMA registration and IRQ dispatching
*
* MA 02110-1301, USA.
*/
-#ifndef __ASM_ARCH_MXC_DMA_H
-#define __ASM_ARCH_MXC_DMA_H
+#ifndef __MACH_DMA_V1_H__
+#define __MACH_DMA_V1_H__
+
+#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
#define IMX_DMA_CHANNELS 16
int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-#endif /* _ASM_ARCH_MXC_DMA_H */
+#endif /* __MACH_DMA_V1_H__ */
# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
obj-$(CONFIG_MXC_TZIC) += tzic.o
-obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
-obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
obj-$(CONFIG_MXC_PWM) += pwm.o