powerpc/85xx: Change deprecated binding for 85xx-based boards
authorBradley Hughes <bhughes@silicontkx.com>
Wed, 21 Jul 2010 12:04:06 +0000 (12:04 +0000)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 4 Aug 2010 19:22:04 +0000 (14:22 -0500)
The "fsl,85..." style compatible binding was to be deprecated
some time ago.  This patch corrects existing occurrences of
the incorrect binding.  The memory-controller and
l2-cache-controller are the only affected nodes.

Signed-off-by: Bradley Hughes <bhughes@silicontkx.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/boot/dts/mpc8540ads.dts
arch/powerpc/boot/dts/mpc8541cds.dts
arch/powerpc/boot/dts/mpc8544ds.dts
arch/powerpc/boot/dts/mpc8548cds.dts
arch/powerpc/boot/dts/mpc8555cds.dts
arch/powerpc/boot/dts/mpc8560ads.dts
arch/powerpc/boot/dts/mpc8568mds.dts

index 9dc2929..8d1bf0f 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8540-memory-controller";
+                       compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8540-l2-cache-controller";
+                       compatible = "fsl,mpc8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 9a3ad31..87ff965 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8541-memory-controller";
+                       compatible = "fsl,mpc8541-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8541-l2-cache-controller";
+                       compatible = "fsl,mpc8541-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 98e94b4..d793968 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8544-memory-controller";
+                       compatible = "fsl,mpc8544-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8544-l2-cache-controller";
+                       compatible = "fsl,mpc8544-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 0f52624..a17a557 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8548-memory-controller";
+                       compatible = "fsl,mpc8548-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8548-l2-cache-controller";
+                       compatible = "fsl,mpc8548-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K
index 065b2f0..5c5614f 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8555-memory-controller";
+                       compatible = "fsl,mpc8555-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8555-l2-cache-controller";
+                       compatible = "fsl,mpc8555-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index a5bb1ec..6e85e1b 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8540-memory-controller";
+                       compatible = "fsl,mpc8540-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8540-l2-cache-controller";
+                       compatible = "fsl,mpc8540-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x40000>; // L2, 256K
index 92fb178..30cf0e0 100644 (file)
                };
 
                memory-controller@2000 {
-                       compatible = "fsl,8568-memory-controller";
+                       compatible = "fsl,mpc8568-memory-controller";
                        reg = <0x2000 0x1000>;
                        interrupt-parent = <&mpic>;
                        interrupts = <18 2>;
                };
 
                L2: l2-cache-controller@20000 {
-                       compatible = "fsl,8568-l2-cache-controller";
+                       compatible = "fsl,mpc8568-l2-cache-controller";
                        reg = <0x20000 0x1000>;
                        cache-line-size = <32>; // 32 bytes
                        cache-size = <0x80000>; // L2, 512K