MIPS: Install handlers for software IRQs
authorKevin Cernekee <cernekee@gmail.com>
Sat, 16 Oct 2010 21:22:33 +0000 (14:22 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 25 Jul 2011 16:26:54 +0000 (17:26 +0100)
BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/irq_cpu.c

index 6e71b28..191eb52 100644 (file)
@@ -103,14 +103,12 @@ void __init mips_cpu_irq_init(void)
        clear_c0_status(ST0_IM);
        clear_c0_cause(CAUSEF_IP);
 
-       /*
-        * Only MT is using the software interrupts currently, so we just
-        * leave them uninitialized for other processors.
-        */
-       if (cpu_has_mipsmt)
-               for (i = irq_base; i < irq_base + 2; i++)
-                       irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
-                                                handle_percpu_irq);
+       /* Software interrupts are used for MT/CMT IPI */
+       for (i = irq_base; i < irq_base + 2; i++)
+               irq_set_chip_and_handler(i, cpu_has_mipsmt ?
+                                        &mips_mt_cpu_irq_controller :
+                                        &mips_cpu_irq_controller,
+                                        handle_percpu_irq);
 
        for (i = irq_base + 2; i < irq_base + 8; i++)
                irq_set_chip_and_handler(i, &mips_cpu_irq_controller,